Silicon carbide bipolar junction transistors (SiC BJTs) are high-performance power devices having low on-state and switching losses and are also capable of high-temperature operation thanks to the high breakdown electric field, high thermal conductivity and high saturated drift velocity of electrons in SiC. SiC is a wide bandgap semiconductor and may advantageously be used for manufacturing devices for high power, high temperature and high frequency applications.
The use of high power SiC BJTs can e.g. decrease the energy loss, the device size and the weight of switch-mode power conversion (SMPC) devices, since SiC BJTs have lower conduction and switching losses than conventional silicon devices. SMPC devices are extensively used in a number of electrical energy conversion systems. One example of such system is a Direct Current to Direct Current (DC-DC) electrical energy conversion system. An SMPC device may also be used in other applications, such as Alternating Current (AC) to DC conversion systems, AC-AC conversion systems and DC-AC conversion systems. High power SiC BJTs can also increase power and efficiency of Radio-Frequency (RF) power generators, as well as decrease the size and the weight of such generators.
SiC power devices, such as SiC BJTs, are however vulnerable to device degradation, such as the so-called bipolar degradation phenomenon, which is a deterioration of the device performance under the conditions of minority carrier injection. Thus, implementation of the above mentioned SMPC devices and RF generators comprising SiC BJTs is usually hindered by the instability of the SiC BJTs in the course of long-term operation.
Generally, bipolar degradation in SiC results from the growth of stacking faults (SFs) that is induced by minority carrier injection in the device. The SFs may either exist in as-grown material or originate from basal plane dislocations (BPDs), as a result of BPD splitting into Shockley partials. In case of BPD splitting, one of the partials remains bound to the location of the BPD whereas the other partial may travel tens or even hundreds of microns in the device as long as minority carriers are provided to the leading edge of the partial. The glide of a partial dislocation occurs in general within the basal (0001) crystal plane. The (0001) plane portion between the two partials will then represent a stacking fault.
The stacking faults may then form resistive barriers for current flow in the device and create channels for fast minority carrier recombination. The growth of stacking faults therefore suppresses vertical transport of minority carriers in the device and increases the on-state forward voltage drop. In BJTs, stacking faults also degrade the performance. In particular, the growth of SFs increases the on-state resistance and decreases the emitter current gain. Thus, there is a need to provide high-power devices that are free (or at least with a reduced number) of BPDs at least in the active parts or regions of the devices, i.e. at least in those parts of the device that are subject to minority carrier injection.
The manufacturing of stable, high power, SiC switching devices can have substantially large crystal areas that are free from defects potentially deteriorating their performance. On-state current densities in high-voltage high-power SiC devices typically range between 100 A/cm2 and a few hundred A/cm2. For example, the current densities for high power BJTs may be selected between 100 and 200 A/cm2 for a blocking voltage of 1200 V. A high-power device rated at 10 A may therefore cover about 5 mm2 and devices operating at higher currents may take up even larger areas. However, a standard commercial-grade epitaxy provides a BPD density in the order of 100-200 cm−2, thereby resulting in about five or more BPDs in average within the device area. There is therefore a need of providing manufacturing methods that yield high-power devices free of BPDs, or at least with a reduced number of BPDs.
For example, some known methods can be based on a defect-selective etch of SiC substrates prior to epitaxial growth. The selective etch forms etch-generated structures from at least any basal plane dislocation reaching the substrate surface, i.e. etch pits of a few microns deep around each dislocation. Although the BPD density may be reduced in the epitaxial layer, the known methods can present the drawback that the layer morphology resulting from the defect-revealing etch is deteriorated. As the total etch pit density in SiC substrates may exceed 1000/cm2, any subsequent portions in the semiconductor process is rendered very complicated.
Thus, there is a need for providing new high-power SiC BJTs and new methods of manufacturing such BJTs that would alleviate at least some of the above-mentioned drawbacks.